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A New Test Data Compression Scheme | Zhang | Journal of Computers
Journal of Computers, Vol 6, No 7 (2011), 1297-1301, Jul 2011
doi:10.4304/jcp.6.7.1297-1301

A New Test Data Compression Scheme

Ling Zhang, Jishun Kuang

Abstract


With the improvement of technology, more cores are placed on a single chip to form a system. The volumes of test data becomes a challenges for circuits test. The paper presents a test data compression which uses hybrid prefix code and a new test set regenerating algorithm. In essence, the technique uses two formats of prefix to encode for the new regenerated test set, and the regenerated test set is better suitable to our compression scheme. So it gain better compression ratio.  Experimental results show that the proposed compression solution could re duce test data volume effectively with a simple decoding architecture.


Keywords


hybrid prefix code, embedded core testing, test data compression, test regeneration

References


[1] M. Tehranipoor, M. Nourani, K. Chakrabarty. “Nine-Coded Compression Technique for Testing Embedded Cores in SoCs”, IEEE transactions on very large scale integration(VLSI) systems. Vol.13,2005,pp 719-731.

[2] Janusz Rajski, Jerzy Tyszer, Mark Kassab and Nilanjan Mukherjee. “Embedded Deterministic test”, IEEE transactions on computer-aided design of integrated circuits and systems, Vol.23, No.5 2004, pp,776-792.

[3] F. Hsu,K.Butler, and J. Patel, “A case study on the implementation of the Illinois scan architecture,” in proc. Int. Test Conf. (ITC’01),2001, pp.538-547.

[4] Laung-Terng Wang, Zhigang Wang, Xiaoqing wen,etc. “VirtualScan: Test Compression Technology Using Combinatioal Logic and One-Pass ATPG”, IEEE Design & Test of Computers.2008.pp.122-129 http://dx.doi.org/10.1109/MDT.2008.56
http://dx.doi.org/10.1109/MDT.2008.56

[5] A. Chandra, A. Chandrabarty, “a Unified Approach to Reduce SOC Test Data Volum, Scan Power and Testing Time”,IEEE Transactions on Computer-aided design of integrated circuits and system. Vol.22.No.3, 2003, PP: 352-362

[6] A.Chandra, K.Chakrabarty, “System-on-a-chip Test-data Compression and Decompression Integrated Circuits and Systems” IEEE transaction on computer-Aided design of integrated circuits and systems. Vol.20, 2001, pp.355-368.

[7] A.Chandra, K.Chakrabarty. “Frequency-diredted Run-length(FDR) Codes with Application to System-on-a-Chip Test Data Compression”. Proceedings of 19th IEEE VLSI Test Symposium(VTS2001).2001pp. 42-47.

[8] A.H.EL-Maleh, “Test data compression for system-on-a-chip using extended Frequency-Directed Run-Length Code”. IET Computers & Digital Techniques. 2008, pp. 155-163.

[9] NOURANI M, Tehranipour. M, “RL-Huffman encoding for test compression and power reduction in scan applicaiton”, ACM trans.Des. AUTOM. Electron. Syst. 2005, 10, (1), pp. 91-115 http://dx.doi.org/10.1145/1044111.1044117

[10] JAS A., GOSH-DASTIDAR J., NG M., TOUBA N.: ‘An effcient test vector compression scheme using selective Huffman coding’, IEEE Trans. Comput. Aided Des., 2003, 22, (6), pp. 797–806

[11] A. Jutman, Igor. Alekejev, J. Raik, etc, “Reseeding using Compaction of Pre-Generated LFSR Sub-Sequences”, IEEE. 2008. pp: 1290-1295

[12] M. Knieser, F. Wolff, C.Papachristou, D.Wyer, and D. McIntyre, “A technique for high ratio LZW compression,” in Proc. Design Automation Test in Europe, 2003, pp. 116-121.

[13] EL-MALEH A., OSAIS Y.E.: ‘Test vector decomposition-based static compaction algorithms for combinational circuits’,ACM Trans. Des. Autom. Electron. Syst., 2003, 8, (4),pp. 430 – 459

[14] EL-MALEH A., AL-SUWAIYAN A.: ‘An effcient test relaxationtechnique for combinational and full-scan sequentialcircuits’. VTS ‘02: Proc. 20th IEEE VLSI Test Symp.,Washington, DC, USA, 2002, p. 53

[15] Ilker Hamzaoglu and Janak H. Patel, “New Techniques for Deterministic Test Pattern Generation,” Proceedings of the VLSI Test Symposium,1998, pp. 446-452

[16] I.Hamzaoglu and J.H.Patel, “Test set compaction algorithms for combinational circuits,” in Proc. Int,Conf. Computer-Aided Design,1998, pp,283-289

[17] A.H.EL-Maleh, “efficient test compression technique based on block merging”, IET compter& Digital Techniques.2007.pp:327-335.


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