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Electrical isolation of dislocations in Ge layers on Si(001) substrates through CMOS-compatible suspended structures - Abstract - Science and Technology of Advanced Materials - IOPscience
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Electrical isolation of dislocations in Ge layers on Si(001) substrates through CMOS-compatible suspended structures

Vishal Ajit Shah, Maksym Myronov, Chalermwat Wongwanitwatana, Lewis Bawden, Martin J Prest, James S Richardson-Bullock, Stephen Rhead, Evan H C Parker, Terrance E Whall and David R Leadley

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Paper

Suspended crystalline Ge semiconductor structures are created on a Si(001) substrate by a combination of epitaxial growth and simple patterning from the front surface using anisotropic underetching. Geometric definition of the surface Ge layer gives access to a range of crystalline planes that have different etch resistance. The structures are aligned to avoid etch-resistive planes in making the suspended regions and to take advantage of these planes to retain the underlying Si to support the structures. The technique is demonstrated by forming suspended microwires, spiderwebs and van der Pauw cross structures. We finally report on the low-temperature electrical isolation of the undoped Ge layers. This novel isolation method increases the Ge resistivity to 280 Ω cm at 10 K, over two orders of magnitude above that of a bulk Ge on Si(001) layer, by removing material containing the underlying misfit dislocation network that otherwise provides the main source of electrical conduction.


PACS

68.55.Ln Defects and impurities: doping, implantation, distribution, concentration, etc.

81.65.Cf Surface cleaning, etching, patterning

73.61.Cw Elemental semiconductors

68.35.B- Structure of clean surfaces (and surface reconstruction)

Subjects

Semiconductors

Surfaces, interfaces and thin films

Dates

Issue 5 (October 2012)

Received 15 July 2012, accepted for publication 21 October 2012

Published 26 November 2012

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