Today’s System-on-Chip (SoC) represent high-complexity and it is moving towards the challenge of huge test patterns, more accessing time and larger power consumption. Test data compression is done to improve the test quality. This study presents a test pattern compression by the usage of suitable clustering technique and its corresponding decompression scheme. This scheme includes compression and decompression achieved by LFSR reseeding. Test data compression is widely used in the industry nowadays to reduce the amount of test data stored on the ATE and to decrease testing time. The proposed method requires no special ATPG. The proposed method is validated by the simulation and synthesis output.