This article is part of the series Design Methods for DSP Systems.

Open Access Research Article

A Fully Automated Environment for Verification of Virtual Prototypes

P Belanović*, B Knerr, M Holzer and M Rupp

Author Affiliations

Institute of Communications and Radio Frequency Engineering, Vienna University of Technology, Vienna 1040, Austria

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EURASIP Journal on Advances in Signal Processing 2006, 2006:032408  doi:10.1155/ASP/2006/32408


The electronic version of this article is the complete one and can be found online at: http://asp.eurasipjournals.com/content/2006/1/032408


Received: 15 October 2004
Revisions received: 29 March 2005
Accepted: 25 May 2005
Published: 18 May 2006

© 2006 Belanović et al.

This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

The extremely dynamic and competitive nature of the wireless communication systems market demands ever shorter times to market for new products. Virtual prototyping has emerged as one of the most promising techniques to offer the required time savings and resulting increases in design efficiency. A fully automated environment for development of virtual prototypes is presented here, offering maximal efficiency gains, and supporting both design and verification flows, from the algorithmic model to the virtual prototype. The environment employs automated verification pattern refinement to achieve increased reuse in the design process, as well as increased quality by reducing human coding errors.

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