It is the cache of http://www.mecs-press.org/ijigsp/ijigsp-v4-n4/v4n4-1.html. It is a snapshot of the page. The current page could have changed in the meantime.
Tip: To quickly find your search term on this page, press Ctrl+F or ⌘-F (Mac) and use the find bar.

International Journal of Image, Graphics and Signal Processing(IJIGSP)

International Journal of Image, Graphics and Signal Processing (IJIGSP)

ISSN: 2074-9074(Print), ISSN: 2074-9082 (Online)

Publisher: MECS
  • IJIGSP Vol.4, No.4, May 2012

Design and Implementation of a Power Efficient Pulse-shaping Finite Impulse Response Filter on a Field Programmable Gate Array Chip

 
Full Text (PDF, 2059KB), PP.1-10  
Author(s)  
Puja Kumari,Rajeev Gupta,Abhijit Chandra  
Index Terms  
Finite Impulse Response (FIR) filter,Power efficiency,Pulse-shaping filter,Raised Cosine (RC) filter  
Abstract  
This paper presents one novel algorithm for minimization of non-zero coefficients of Finite Impulse response (FIR) pulse-shaping filter, mostly employed in practical digital communication system to alleviate the difficulties resulting from Inter Symbol Interference (ISI), followed by its hardware optimization on a Field Programmable Gate Array (FPGA) chip . Filter performance has been demonstrated through the inclusion of impulse response, magnitude spectrum and requirement of various hardware blocks. The supremacy of our algorithm has been substantiated by comparing its performance with other existing models of different length. From the simulation results, it has been concluded that the proposed FIR filter provides a considerable reduction in the number of non-zero coefficients without affecting its performance significantly.
 
Reference  
[1] Simon Haykin, “Communication Systems”, John Wiley and Sons, 4th Edition, 2001.
[2] K. Feher, “Wireless Digital Communications- Modulation and Spread Spectrum Applications”, Prentice Hall of India, pp. 119-125, 2005.
[3] John G. Proakis, “Digital Communications”, Tata McGraw Hill Book Co 3rd Edition, Chapter 9, 2001.
[4] Stanley A. White, “Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review”, IEEE ASSP Magazine, July, 1989.
[5] M.Rawski, P. Tomaszewicz, H. Selvaraj and T. Luba, “Efficient Implementation of Digital Filters with the use of Advanced Synthesis Methods Targeted FPGA Architectures”, in Proc. 8th Euromicro Conference on Digital System Design, IEEE, Computer Society, 2005.
[6] E. Lee, “Programmable DSP Architectures: Part II”, IEEE Transactions on Acoustics, Speech and Signal Processing Magazine, pp. 4-14, 1989.
[7] J. R. Choi, L.H. Jung, S.W. Jung and J. H. Choi “Structured Design of a 288 tap FIR Filter by optimized partial tree compression”, IEEE Solid State Circuits, vol. 32, pp. 468-476, March 1997.
[8] S. K. Mitra, “Digital Signal Processing: A Computer based Approach”, Tata McGraw Hill Co., 2001
[9] M. A. M Eshtawie and M. B. Othman, “An Algorithm Proposed for FIR Filter coefficients representation”, in Proc. International Journal of Applied Mathematics and Computer Sciences, vol. 4, pp. 24-30, 2008..
[10] C. J. Nicol, P. Larsson, K. Azadet and J.H. O’Neill, “ A Low Power 128 tap Digital Adaptive Equalizer for Broadcast Modem”, IEEE Solid State Circuits, vol. 32, pp. 1777-1789, Nov-1997.
[11] A. Chandra, S. Chattopadhyay and S.K.Sanyal, “An Efficient Algorithm to minimize the number of coefficients of FIR Pulse Shaping Filter”, in Proc. Annual IEEE India Conference (INDICON 2010), December 17-19, 2010, Kolkata
[12] S. Creaney and I. Kostarnov “Zero ISI on Raised Cosine Pulse Shaping”, Springer, 2011.
[13] Richard G. Lyons, “Understanding Digital Signal Processing”, Pearson Education Inc., 3rd Edition, 2011.
[14] Li Tan, “Digital Signal Processing: Fundamentals and Applications”, Academic Press, 1st Edition, 2008.
 
Citation  
Puja Kumari,Rajeev Gupta,Abhijit Chandra,"Design and Implementation of a Power Efficient Pulse-shaping Finite Impulse Response Filter on a Field Programmable Gate Array Chip", IJIGSP, vol.4, no.4, pp.1-10, 2012.