The aim of this study is to implement enhanced test data compression of conflict bit using clustering technique. Huge test patterns, larger power consumption and more accessing time are the various challenges encountered by present System on Chip (SOC) design. Various compression techniques have been developed to minimize the huge test patterns by reducing the size of the data which saves space and transmission time. Test quality of the test pattern can be improved by test data compression. By finding the proper conflict bit (‘U’) the proposed algorithm generates test patterns having high reduction in test compression. Small numbers of test patterns are generated using clustering technique. With proper test pattern clustering it is possible to achieve high level of compression. Validation of the proposed method is found by experimental results on ISCAS’89 and shows that compression ratio is achieved by 79% with less conflict test pattern.