We present AVSynDEx (concatenation of AVS 
SynDEx), a rapid prototyping process aiming to the implementation of digital signal processing applications on mixed architectures (multi-DSP 
FPGA). This process is based on the use of widely available and efficient CAD tools established along the design process so that most of the implementation tasks become automatic. These tools and architectures are judiciously selected and integrated during the implementation process to help a signal processing specialist without relevant hardware experience. We have automated the translation between the different levels of the process to increase and secure it. One main advantage is that only a signal processing designer is needed, all the other specialized manual tasks being transparent in this prototyping methodology, hereby reducing the implementation time.
This article is part of the series Implementation of DSP and Communication Systems.
Research Article AVSynDEx: A Rapid Prototyping Process Dedicated to the Implementation of Digital Image Processing Applications on Multi-DSP and FPGA Architectures
CNRS UMR IETR (Institut en Electronique et Télécommunications de Rennes), INSA Rennes, 20 avenue des Buttes de Coësmes, CS 14315, Rennes Cedex 35043, France
EURASIP Journal on Advances in Signal Processing 2002, 2002:896506 doi:10.1155/S1110865702205016
The electronic version of this article is the complete one and can be found online at: http://asp.eurasipjournals.com/content/2002/9/896506
| Received: | 31 August 2001 |
| Revisions received: | 12 May 2002 |
| Published: | 1 September 2002 |
© 2002 Fresse et al.
close
Sign up to receive new article alerts from EURASIP Journal on Advances in Signal Processing
